Multi-stage ADC's have been used for some time in situations where high resolutions are required. One common type of multi-stage converter is referred to as a subranging converter. Subranging converters provide high resolution with significantly fewer comparators and simpler logic than single-stage converters, but give up some of the inherently higher speed capabilities of single-stage parallel, or flash, converters.
FIG. 1 shows a block diagram representation of a generic pipelined multi-stage ADC for converting an analog signal to an m-bit value or series of m-bit values. The analog input V.sub.in, is digitized through a series of multi-bit flash conversions, each of fewer than m bits. The three blocks 12A, 12B, and 12C are identical, and an expanded block diagram for those blocks is shown as block 12 in FIG. 2. Each block 12 contains a sample-and-hold amplifier (SHA) 14, a flash converter 16, and a digital-to-analog converter (DAC) 18. The block 12 provides as its output a RESIDUE OUT signal which is the difference between the output of SHA 14 and DAC 18, and is thus a representation of the error in the digital output of flash converter 16. Returning to FIG. 1, block 22 contains a flash converter only. Each of the flash converters of blocks 12A, 12B, 12C and 22 provides an X-bit representation of the input signal to that particular block. Traditionally, the range of each stage is greater than one LSB (least significant bit) of the previous stage, for error correction.
As FIG. 1 also shows, a digital delay structure is necessary to facilitate the generation of one binary word to represent the sampled analog input signal. This digital delay structure is provided by the various registers 24A-24F. Correction logic 26 combines the outputs from registers 24D-24F, and from converter 22, to provide the digital output code, which in this case is a (4X-3)-bit representation.
During operation, each of the first three stages 12A-12C samples and holds the output from the previous stage. Each stage then does a low-resolution analog-to-digital conversion on the sampled signal, and the code produced is converted back to an analog signal by a DAC. The DAC output is subtracted from the sampled input, generating the aforementioned residue signals, each of which is then passed onto the next stage. The residue signal is usually amplified, so that each stage operates with a similar input signal range, improving the tolerance to other sources in any given stage when compared with its predecessor stage. The fourth stage 22 contains an ADC only, since no residue output is generated from this block.
Previous implementations of the architecture of FIG. 1 have relied on the input and residue signals being voltages or charges. This places severe constraints on signal swing with respect to available headroom, and imposes fairly demanding settling time requirements. There is a strong move within the electronics industry toward systems using single supply voltages, such as a single five-volt supply. However, operation of such systems under this constraint is difficult.
The transfer functions of the ADC's are offset by one-half LSB, so that all analog values within a given range centered on a nominal analog value are represented by the same digital code. As shown in FIG. 3, this results in the first code (000) becoming one-half LSB wide, while the last code (111) becomes three-halves LSB wide. In a straight ADC, this does not represent a problem. However, in a pipelined architecture such as that of FIG. 1, where remainders are passed on from one stage to the next, recovery of codes representing inputs near full-scale values will require use of overrange correction codes. This leaves no room for errors at input signals levels near these values.
Further, prior implementations of the architecture of FIG. 1 have either used a dedicated sample-and-hold amplifier up front, followed by a quantizer section, as shown in FIG. 2, or have applied the analog input signal directly into a quantizer section. The timing requirements of the latter type of implementation, in terms of the tolerable skew between the sampling by the SHA and the flash converter, make operation beyond eight to nine bits extremely difficult for high bandwidth input signals.
Accordingly, it is an object of the present invention to provide a multistage ADC architecture which can be operated on a single 5V supply while still allowing substantial analog signal swing.
Another object is to provide an ADC which overcomes some of the speed and settling limitations of voltage mode ADC's.
Another object of the invention is to provide an ADC which has improved error correction when the input is close to full scale.